Light emitting diodes (LEDs) are applied to backlight units of a variety of display devices as well as lighting systems and their applications are extended to more fields. Particularly, LEDs can be driven at relatively low voltage and have high energy efficiency, ensuring their low heat emission, long lifetime, and environmental friendliness. Thus, LEDs are expected to replace most of the current light source devices.
Many methods for fabricating light emitting diodes are known. As an example, a light emitting diode is fabricated by sequentially forming epilayers on a single substrate and forming a plurality of light emitting cells through a series of processes, such as etching and deposition. Light emitting diodes having a multi-cell structure including a plurality of light emitting cells formed on a single substrate are fabricated in various designs, whose examples are illustrated in FIGS. 1 and 2. FIG. 1 is a partial view of a light emitting diode having a multi-cell structure and FIG. 2 is a cross-sectional view of two light emitting cells 10 and 20 of the light emitting diode having a multi-cell structure, taken along line I-I of FIG. 1. As illustrated in FIGS. 1 and 2, a passivation layer 33 is formed to insulate the adjacent light emitting cells 10 and 20 and an interconnection layer 32 is formed on the passivation layer 33 to electrically connect the light emitting cells 10 and 20. The interconnection layer 32 is formed, for example, by a deposition process, such as sputtering or e-beam evaporation, and an etching process. In FIG. 2, reference numerals 1, 16/26, 11/21, 12/22, 13/23, 14/24, and 15/25 denote a substrate, electrodes, buffer layers, N-type semiconductor layers, active layers, P-type semiconductor layers, and transparent electrode layers, respectively. The electrode patterns and the connected state between the electrodes and the interconnection layer may vary, and their examples are illustrated in FIGS. 1 and 2.
As illustrated, when the interconnection layer 32 is formed on the passivation layer 33, many defects are formed in an edge portion of the interconnection layer 32, i.e. around an edge where one facet and the upper surface of each of the light emitting cells meet each other. That is, as illustrated in (a), (b), and (c) of FIG. 3, the edge portion where one facet and the upper surface of each of the light emitting cells meet each other is insufficiently deposited or is exposed during subsequent processing, such as etching, and as a result, a portion 32a, 32b or 32c of the interconnection layer around the edge portion is locally reduced in thickness. When power is supplied to each of the light emitting cells, a relatively large resistance is generated in the portion 32a, 32b or 32c. The large resistance increases the amount of heat generated in the interconnection layer, and as a result, the interconnection layer is electrically disconnected in the portion 32a, 32b or 32c. Thus, there is a need in the art to provide a solution to this problem.